RTL Design Engineer, AI ASICs & Tapeout

Normal Computing seeks an RTL Design Engineer to own digital logic from microarchitecture to tapeout. You will craft synthesizable SystemVerilog, work with verification on debug and coverage, and partner with physical design to meet timing and area constraints.

This role emphasizes architecture decisions and close collaboration across teams. The candidate should have hands-on RTL production experience, a track record of silicon tapeouts, and comfort working where specifications are evolving in