RTL & PD Design Engineer for AI ASICs

Normal Computing is seeking an RTL and PD Design Engineer to take and optimize RTL through synthesis and the backend to produce GDSII ready for tapeout. You will own RTL from microarchitecture to tapeout, writing SystemVerilog, and collaborating with verification engineers to test with both conventional and formal methods.

This role bridges architecture, verification, RTL design, and physical design, requiring close partnership with fab reps and architecture teams to drive design decisions and