Remote Senior Verification Architect - ASIC/FPGA

Fidus is seeking an experienced Verification Designer to own block- and system-level verification for ASIC/FPGA designs, building UVM, formal, and assertion-based environments and driving coverage closure, often working directly with clients on verification strategy.

You bring 8+ years of verification leadership, strong SystemVerilog/UVM fluency, CRV knowledge, and scripting skills to automate tasks across cross-functional teams.