Remote Senior ASIC Design Engineer - AI/HPC Networking

Cornelis Networks is seeking Senior ASIC Design Engineers to advance world‑class SoCs for AI HPC interconnects. You will design RTL in Verilog/SystemVerilog for high‑speed data paths, and collaborate across hardware, firmware and software teams to validate and optimize performance at scale.

Ideal candidates have 8+ years in digital design, strong debugging skills, and experience with timing closure and physical design.