Tensordyne, a Sunnyvale-based AI ASIC startup, seeks an experienced ASIC design engineer to drive microarchitecture and RTL implementation for a high-performance CNN accelerator ASIC. You will integrate CPU and IP blocks, collaborate with physical design, and support timing closure at high frequencies.
The role requires 3+ years in ASIC design with Verilog/SystemVerilog, knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, and AMBA protocols. A BS/MS in EE/CE is preferred.
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