TSMC is seeking a Principal Engineer in California to lead physical design activities for advanced processing technologies. You will work on block level floor planning, clock tree synthesis, place-and-route, RC extraction, STA, and timing closure with standard EDA tools and scripting.
The role requires a bachelor's degree in Electrical or Electronic Engineering and at least five years of related experience, including full-cycle physical design and PPA analysis of CPU blocks in N7/N5 and below.
#J-18808-LjbffrPrincipal VLSI Physical Design Engineer in ca at Unknown Company
This position is listed as full time and onsite.