Cadence Design Systems is leading the way in EDA tools for contemporary chip design, with a focus on scalable compilers and AI-enabled verification. The Senior Engineer role centers on evolving the SystemVerilog compiler to meet multi-billion gate challenges, while optimizing performance and memory usage in C/C++.
Join a team that tackles next-gen NPUs and AI-driven silicon, delivering technology that powers automotive, 5G, and hyperscale computing.
#J-18808-LjbffrPrincipal SystemVerilog Compiler Engineer for AI-Scale ICs in burlington at Unknown Company
This position is listed as full time and onsite.