Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP that powers rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and push first-pass silicon success across analog/digital boundaries.
You will collaborate with PHY analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks used in PCIe Gen6/Gen7, UALink, UCIe, and Ethernet
#J-18808-LjbffrPrincipal SerDes/PHY Verification Architect in san jose at Unknown Company
This position is listed as full time and onsite.