Principal RTL Design Engineer - Hybrid

Cypress HCM is seeking an experienced RTL design lead for ASIC/FPGA developments in a hybrid San Jose, CA Hillsboro, OR area. You will drive architecture decisions, mentor teams, and collaborate across verification, implementation, and customer engagements.

The role requires 8+ years of logic design, expertise in Verilog/SystemVerilog and UVM, and strong memories/interfaces knowledge. A BSEE or MSEE is preferred, with competitive benefits and stock options.