Principal Post-Silicon Validation Engineer

Principal Post-Silicon Validation EngineerAstera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize real silicon in the lab, and drive root-cause analysis of the toughest system-level issues.As AI workloads scale into rack-level infrastructure, every link has to perform flawlessly. Your work will directly shape the quality, performance, and time-to-market of the products that connect the world's most advanced AI platforms, in a hyper-growth company where your technical judgment carries real weight.Key ResponsibilitiesArchitect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production releaseDefine test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teamsLead lab bring-up of new silicon, including board, firmware, and software readinessDebug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundaryCharacterize high-speed serial link performance, including margining, signal integrity, and compliance, across process, voltage, and temperaturePartner with design and DFT teams to feed findings back into current and future product generationsDevelop scalable validation automation frameworks and test content using Python and C/C++Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughputAnalyze large validation datasets to identify trends, outliers, and risks earlyMentor engineers and set best practices for validation methodology across the teamCollaborate with customers and Field Applications Engineers to reproduce and resolve system-level issuesBasic QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or a related field8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterizationHands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layerProficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power suppliesStrong scripting and programming skills in Python and/or C/C++ for test automationProven ability to debug complex hardware and firmware issues to root causePreferred QualificationsMaster's degree or PhD in Electrical Engineering, Computer Engineering, or a related fieldExperience with PCIe Gen 5 or Gen 6, Ethernet, or retimer productsExperience with SerDes characterization, equalization tuning, and link marginingTrack record of taking multiple products from first silicon to volume productionStrong cross-functional communication skills and the ability to lead without direct authoritySalary range is $207,000 to $230,000 depending on experience, level, and business need.

This role may be eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.