Location: San Jose, CA 95134 or Hillsboro, OR 97006 | Hybrid Remote: 3 days in the office per week
Responsibilities
- Leading RTL design and microarchitecture development for complex digital logic blocks
- Drive architecture decisions through performance, power, and area analysis
- Partner with verification teams to improve test strategies and coverage
- Collaborate with implementation teams to resolve design, timing, and power challenges
- Debug and resolve design issues identified during verification and validation
- Support technical discussions during customer evaluations and engagements
- Assist with product integration and deployment activities
Requirements
- 8+ years of logic design experience – ASIC and/or FPGA development
- Expertise in Verilog/SystemVerilog RTL design and UVM-based verification environments
- Background in high-speed memory or interface technologies
- Experience with industry-standard simulation and verification tools (Questa, Incisive, VCS)
- Proficiency in scripting languages such as Python, Perl, or TCL
- Experience with synthesis, static timing analysis, and clock/reset domain methodologies
- Experience with on-chip interconnects and industry-standard protocols
- Exposure to advanced SoC or high-performance computing designs
- BSEE and/or MSEE (preferred)
- Competitive medical, dental, vision, and life insurance plans – including HSA and FSA options
- 401K plan with company match
- Employee stock purchase plan (15% discount)
Principal Logic Design Engineer - San Jose in san francisco at Unknown Company
This position is listed as full time and able to be worked remotely.