Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes

Job Description

We are seeking a Principal / Lead DSP & Systems Architect to own the architectural direction of ultra high-speed SerDes platforms targeting 448G per lane and emerging post-448G standards, spanning both electrical (chip-to-chip, backplane, copper cable) and optical (IM-DD and coherent) interfaces. This individual will drive end-to-end link architecture, DSP algorithm design, and ADC/DAC-based transceiver partitioning, serving as the primary technical interface with strategic customers and standards bodies.

The ideal candidate combines deep expertise in high-speed link theory, advanced equalization and FEC, PAM/multi-level and coherent signaling, and hardware‑aware DSP implementation, with a track record of delivering SerDes IP into silicon at the bleeding edge of the wireline and optical roadmap.