Astera Labs in the United States is seeking a Principal Digital Design Engineer to lead front-end circuit design, RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. You will own the front-end from architecture to GDS and drive complex designs to production.
The ideal candidate has deep experience with PCIe, Ualink, Esun, Ethernet, UVM-based verification, and 8+ years in SoC/silicon products. US work authorization is required.
#J-18808-LjbffrPrincipal Front-End Digital Design Engineer - PCIe/NVLink in san jose at Unknown Company
This position is listed as full time and onsite.