Principal FPGA & RTL Design Engineer – Signal Processing

Silvus is looking for a Principal FPGA / RTL Design Engineer - Signal Processing in Irvine, California. The role involves collaboration with the FPGA Engineering team to participate in the entire R&D process from concept to deployment. The successful candidate will have over 10 years of experience in RTL design and FPGA implementations.

This position offers a salary range of $165,000 to $250,000 based on experience and qualifications.