Principal Engineer, SOC DesignSan Jose, California, United StatesAdvancing the World's Technology TogetherOur technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves.
Together, we're building a better tomorrow for our employees, customers, partners, and communities.Principal Engineer, SOC DesignWhat You'll DoThe DRAM Development Lab (DDL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL's vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions.
We are an integral part of Samsung's strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You'll focus on enhancement of memory and storage capability by developing prototype and production controllers.What You BringBachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.Highly motivated with good verbal and written communication skills.Hands on knowledge & experience in ASIC design flow from design to tape out.Experience & Good knowledge in ATE vector generation, testing and silicon bring up.Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.Good understanding of PPA (performance, power, and area) trade-offs.Experience in SoC level synthesis, timing analysis, lint check, CDC checks.Experience in interfacing 3rd party service companies for DFT/PI/PD.Good knowledge and experience in AMBA bus fabric, ARM cores.Self-motivated problem-solver with an ability to work well in a team.You're inclusive, adapting your style to the situation and diverse global norms of our people.An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.You're collaborative, building relationships, humbly offering support and openly welcoming approaches.Innovative and creative, you proactively explore new ideas and adapt quickly to change.Base Pay Range $219,000 - $351,000 USDEqual Opportunity Employment PolicySamsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.Our Commitment to Innovation and FairnessAt Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency.
However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.