Cadence Design Systems is seeking an experienced engineer to advance PCIe AVIP and Virtual Bridge offerings. You will design protocol features, build BFMs and transactors, and ensure scalable verification across emulation platforms.
You will work with cross-functional teams, debug complex issues, and support customer deployments, contributing to high-performance compute, AI, and networking solutions.
#J-18808-LjbffrPrincipal Engineer - PCIe/CXL Emulation & Verification in san jose at Unknown Company
This position is listed as full time and onsite.