Low Power Chip Architect / System EngineerQualcomm Technologies, Inc. is seeking a senior-level Low Power Chip Architect / System Engineer with deep expertise in mixed-signal IC and system design and a proven record of chip-level technical leadership. This is a high-impact role responsible for defining the architecture, driving transistor-level design, and enabling system-level integration of ultra-low-power integrated circuits (ICs) for Robotics and Industrial IoT (IIoT) applications.The successful candidate will bridge high-performance Analog Front Ends (AFEs) with digital logic and firmware, leading programs from initial architecture and specification through simulation, verification, tape-out, and early silicon bring-up. This role requires strong cross-functional collaboration, sound architectural judgment, and the ability to operate effectively in ambiguous environments.** Position requires to be onsite in San Diego, 5 days a week.
**Minimum Qualifications:Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. ORMaster's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. ORPhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.Responsibilities:Architecture & Technical LeadershipDefine and support end-to-end system architecture, including partitioning across analog, digital, firmware, and system domainsDrive architectural trade-offs across power, performance, noise, latency, and silicon areaPartner with chip leads and system leads from concept definition through silicon bring-up and validationMixed-Signal Design & IntegrationLead feasibility studies and transistor-level design of mixed-signal building blocks including ADCs, DACs, PLLs/DLLs, LDOs, and SerDesArchitect and integrate ultra-low-power AFEs optimized for battery-operated IIoT and Robotics sensor ASICsDrive full-chip execution in collaboration with internal teams and third-party IP vendors and design housesModeling, Verification & Silicon ExecutionDevelop behavioral and system-level models using MATLAB/Simulink (or equivalent tools) to evaluate noise, linearity, and SNRPerform comprehensive pre-silicon verification across PVT corners using industry-standard simulatorsSupport post-silicon bring-up, characterization, and reliability qualification, including HTOL and burn-inCollaborate with packaging, test, and system teams to ensure successful productizationSystem & Application EnablementSupport multi-modal sensor data acquisition, sensor fusion, and edge AI inference workflowsContribute to hardware–software integration for efficient system-level deploymentPreferred Qualifications:Ph.D. in Electrical Engineering (or related field) with 8+ years of post-degree industrial IC/system design experience ORM.S.
in Electrical Engineering (or related field) with 10–12+ years of industrial IC/system design experienceStrong expertise in low-power analog and mixed-signal (AMS) IC designHands-on experience with Cadence Virtuoso, AMS sims, Verilog and related analog design toolsProficiency with Spectre, HSPICE, and board-level simulation methodologiesSolid understanding of PDKs, LVS, DRC, and PEX flowsProven experience with ESD and reliability standards (HBM, CDM, TLP)Advanced academic background in Electrical Engineering or a closely related fieldExtensive industry experience in mixed-signal IC and system-level designDemonstrated experience as a Chip Lead, System Architect, or Technical LeadProven ability to drive end-to-end silicon programs from concept to productionStrong capability to work independently and provide technical direction with minimal supervisionExperience with digital design flows, including synthesis and timing analysisFamiliarity with firmware development and software integrationWorking knowledge of embedded interfaces such as I2C, I3C, SPI, and MIPIProficiency in Python or similar scripting languagesExperience with deep submicron CMOS technologies and low-power fabrication processesExposure to IC packaging, board-level validation, and system bring-upBackground in sensor systems, sensor fusion, or edge AI applicationsSoft Skills:Strong technical leadership and ownership mindsetExcellent cross-functional communication and collaboration skillsAbility to mentor and guide engineers across analog, digital, layout, and system domainsStrong analytical and problem-solving abilitiesComfortable making architecture-level decisions under ambiguityEffective at managing external vendors, IP providers, and design partnersResults-driven with a strong focus on execution and qualityPay range and Other Compensation & Benefits :$192,000.00 - $288,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.
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