Principal Engineer, Design VerificationThe Data Center and Energy team is seeking a highly experienced Principal Design Verification Engineer to provide strategic leadership and technical direction across our Power Controller BU portfolio at ADI's Durham, NC facility. As a technical leader, the candidate will lead a small team of verification engineers while driving DV strategy, methodology innovation, and execution excellence across multiple projects. This role combines hands-on technical expertise with leadership responsibilities, requiring the candidate to define and implement state-of-the-art verification methodologies, mentor team members, and ensure verification quality across the entire product portfolio.Analog Devices offers a Flexible Work policy which includes remote work days and alternative schedule options.Key ResponsibilitiesDefine and implement the DV strategy for the group, ensuring alignment with business objectives and product roadmapsDevelop comprehensive DV plans for multiple projects as requiredDrive adoption of state-of-the-art DV methodologies including advanced UVM architectures, formal verification, portable stimulus (PSS), and AI/ML-assisted verification techniquesEstablish verification metrics, KPIs, and quality gates to measure verification progress and coverage closureLead and mentor a small team of design verification engineers, providing technical guidance and career development supportConduct code reviews, testbench architecture reviews, and methodology assessmentsCollaborate on recruiting, interviewing, and onboarding new verification talentArchitect scalable, reusable verification infrastructure across multiple projects and product generationsDrive evaluation and adoption of new EDA tools, verification IP, and emerging methodologiesLead development of advanced testbench components including UVM environments, formal verification approaches, and mixed-signal verification solutionsSupport all projects across the portfolio with DV planning, execution oversight, and technical problem-solvingPartner with analog and digital design teams to ensure seamless integration and verification of mixed-signal designsInterface with product engineering, applications, and silicon validation teamsRepresent the verification team in project reviews, design reviews, and executive briefingsDevelop and document best practices, guidelines, and playbooks for the verification organizationStay current with industry trends and drive adoption of relevant innovationsMinimum QualificationsBachelor's or Master's degree in Electrical or Computer Engineering10+ years of hands-on experience in SystemVerilog/UVM-based verification3+ years of technical leadership experience, including mentoring engineers, leading verification efforts on complex projects, or managing small teamsDemonstrated experience architecting verification environments for complex mixed-signal SoCs or power management ICsProven track record of defining and implementing DV strategies across multiple concurrent projectsExpert-level proficiency in EDA tools and automation (Python, TCL, Perl, Shell) for building verification infrastructure and flowsExperience with formal verification methodologies and tools (JasperGold, VC Formal, or equivalent)Strong understanding of coverage-driven verification, including functional coverage modeling and closure strategiesExcellent communication skills with the ability to present technical content to diverse audiences, including executivesPreferred QualificationsExperience with portable stimulus standard (PSS) and graph-based verification approachesDeep knowledge of analog/mixed-signal verification techniques including SV-RNM modelingExperience with verification of ARM/RISC-V based sub-systems or complex SoCsExpertise in power management IC verification, including multiphase DC-DC controllers, voltage regulators, and power sequencingExperience with voltage interface protocols such as PMBUS, AVS, SVID, SVI3, I2C, SPIKnowledge of emulation and FPGA prototyping methodologies for early software enablementRTL design experience providing strong design-for-verification perspectiveExperience building and scaling verification teams or capabilitiesTrack record of driving process improvements that measurably improved verification quality or efficiencyAI/ML tools for verification – keen interest and experience leveraging AI for coverage closure, test generation, debug, or productivity improvementsProficiency with multiple verification platforms (Cadence, Synopsys, Mentor/Siemens)Experience with continuous integration/continuous verification (CI/CV) pipelinesFamiliarity with cloud-based verification and distributed simulation/regression managementVersion control expertise (Git, Perforce) and collaborative development workflowsVerilog, C/C++, SystemC for modeling and verificationStrong analytical and debug skills with ability to drive complex issues to resolutionAnalog Devices is an equal opportunity employer.
We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.EEO is the Law: Notice of Applicant Rights Under the Law.Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days