Principal Engineer, Design Verification (NPU)Employment Type: Contract Location: Mountain View, CA (Hybrid)Project Description The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role drives verification excellence for a state-of-the-art Neural Processing Unit (NPU) by developing comprehensive testbenches and validation methodologies to ensure functional correctness and performance.
The role also leads development of verification infrastructure, including scalable regression frameworks and coverage-driven methodologies to deliver a safety-critical NPU meeting automotive industry requirements.ResponsibilitiesVerification Planning & Strategy (40%)Develop verification plans and test plans for NPU functional blocks and system-level integrationDefine verification milestones, coverage goals, and success criteriaCreate verification strategies for AI workloads including convolution engines, matrix multiply units, and activation functionsTestbench Development & Implementation (40%)Design and implement System Verilog/UVM testbenches for NPU verificationDevelop constrained random test generators for neural network inference pipelinesCreate reference models and checkers for AI workload validationBuild verification environments for memory subsystems, DMA controllers, and system interconnectsImplement functional and code coverage methodologiesSystem Integration & Performance Verification (20%)Verify AXI4/AHB protocol compliance and system-level interfacesValidate timing, throughput, and power consumption requirementsMaintain regression test suites for CICollaborate on hardware-software co-verificationSupport FPGA prototyping and emulation platformsEnsure compliance with ISO 26262 functional safety requirementsSkillsMust HaveExpert communicator across global and cross-functional teamsStrong analytical, debugging, and system-level problem-solving skillsAbility to lead complex technical initiatives without direct authorityQuality-driven mindset focused on correctness, robustness, and coverageCollaborative approach across hardware, software, verification, and safety teamsExpert System Verilog and UVM-based verificationCoverage-driven, constrained-random, and formal verificationVerification automation using Python/PerlFPGA prototyping and emulation-based validationNice to HaveAutomotive functional safety (ISO 26262)Power-aware and low-power verification techniquesGenAI-assisted verification workflowsVerification of AI accelerators, NPUs, and complex digital subsystemsAXI4/AHB protocol and memory subsystem verification