Celero Communications, Inc. in Irvine, CA is seeking a Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs powering AI and hyperscale optical networking.
You will drive silicon characterization and readiness for customer deployment. You will collaborate across Architecture, RTL, Firmware, Systems and Customers, shaping validation strategy, building automation frameworks in Python, and ensuring production-ready validation
#J-18808-LjbffrPrincipal DVT Engineer – Post-Silicon for AI DSPs in irvine at Unknown Company
This position is listed as full time and onsite.