Celero Communications, Inc. is seeking a Principal Design Validation & Test (DVT) Engineer to lead post-silicon validation for next-generation coherent DSP ASICs.
You will drive silicon characterization, enable first silicon bring-up, and ensure customer-ready production, collaborating across Architecture, RTL, Firmware, and Systems teams. You will develop validation infra, automation, and test plans, validating PCIe, Ethernet, SerDes, CXL, and more while guiding senior engineers.
#J-18808-LjbffrPrincipal DVT Engineer: ASIC Post-Silicon Validation in irvine at Unknown Company
This position is listed as full time and onsite.