Principal DV Engineer: SerDes/PHY IP for AI Systems

Astera Labs is seeking a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success across PCIe Gen 6/7, UALink, UCIe, and Ethernet interfaces.

You will collaborate with analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks and guide the DV team through tape-out readiness and post-silicon validation.