Principal Digital Verification Engineer

Principal Digital Verification Engineer – SystemVerilog / UVM / SVA / ASIC / Optical Networking

We are currently partnered with a telecommunications technology organisation developing advanced optical transmission and networking solutions. This opportunity focuses on digital verification for high-speed optical networking products, with responsibility for defining verification strategies, validating digital subsystems, optimising verification environments and collaborating with design engineers, systems engineers and architects.

Key responsibilities

• Analyse project architectures and functional requirements in collaboration with systems engineers and architects.
• Validate digital subsystems using simulation, formal verification and coverage methodologies.
• Create, review and optimise simulation environments, test scenarios, functional coverage plans and formal verification test plans.
• Lead focused technical initiatives and mentor team members where required.
• Estimate project schedules, track progress against approved plans and communicate status updates.
• Lead verification activities as an ASIC Verification Prime when assigned.
• Participate in architectural and design reviews to identify verification impacts and opportunities to improve coverage and schedule execution.

Key requirements

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, Computer Science or another applicable scientific discipline.
• 12+ years of experience using SystemVerilog, UVM, SVA and major-vendor simulators in digital verification environments.
• Experience with Digital Signal Processing (DSP).
• Experience using Jira for bug tracking.

Keywords

Principal Digital Verification Engineer / Digital Verification / ASIC Verification / ASIC Verification Prime / SystemVerilog / UVM / Universal Verification Methodology / SVA / SystemVerilog Assertions / Digital Design Verification / Functional Verification / Verification Strategy / Functional Coverage / Coverage Planning / Simulation / Formal Verification / Verification Test Plans / Testbench Development / Simulation Environments / Test Scenario Development / Digital Subsystems / Architecture Reviews / Design Reviews / Technical Leadership / Mentoring / Debugging / Optical Networking / Optical Transmission / High-Speed Connectivity / Telecommunications / Digital Signal Processing / DSP / Forward Error Correction / FEC / Jira / Git / Python / Make / Bash / Object-Oriented Programming / OOP / C / C++ / Electrical Engineering / Computer Engineering / Computer Science / Rochester / New York

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