Principal Digital Design Verification Engineer

E-Space in Saratoga, CA is seeking Digital Design Verification Engineers to verify ASICs for satellite and wireless systems. You will work with Verilog, SystemVerilog and UVM, building verification environments and leading code coverage closure for tapeout-ready designs.

Applicants should have 10+ years in semiconductor verification, strong C/C++ skills, and scripting in Python/Perl. Willingness to work extended hours during critical periods is expected.