Principal Digital Design EngineerHybrid role requiring 3 days a week onsite in the office. Reports To: Head of EngineeringPowerLattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry's groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.About the RoleWe are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components.
This role combines deep technical contribution with team leadership, requiring active involvement from microarchitecture definition through RTL development and into back-end implementation and silicon bring-up.Key ResponsibilitiesArchitecture & Hands-On DesignDefine microarchitecture for complex digital blocks and subsystemsActively contribute to RTL development for key componentsDrive design tradeoffs across performance, power, area (PPA), and testabilityRTL Development & IntegrationWrite, review, and integrate high-quality RTLLead block- and chip-level integration, resolving interface and system issuesEnsure designs are clean for lint, CDC/RDC, and synthesisBack-End & Implementation OwnershipEnsure RTL is optimized for synthesis, timing, and physical designWork on scan insertion, test architecture, and coverage closurePerform, review and debug logic equivalence checking (LEC) results between RTL and netlistsDefine and validate timing constraints (SDC) and complete timing closureDrive and implement timing and functional ECOs as neededDesign Quality & SignoffDrive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checksEnsure designs meet functional, timing, power, and test requirementsSupport silicon bring-up, debug, and root-cause analysisCross-Functional CollaborationWork closely with verification, physical design, DFT, and firmware teamsAlign design decisions with verification plans and implementation ConstraintsAct as the technical bridge between front-end and back-end teamsQualificationsThis is a hybrid role requiring 3 days a week onsite at our HQ's in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field10+ years of experience in digital design with significant hands-on RTL developmentProven track record of delivering complex SoC or subsystem designs to tapeoutStrong expertise in:RTL design and microarchitectureSoC integration and standard interfacesHands-on experience with back-end flows, including:Scan insertion and DFT (scan, MBIST, test coverage)Logic equivalence checking (LEC)Static timing analysis (STA) and timing closureTiming constraint development and debug (SDC)Solid understanding of:Clocking, resets, CDC/RDC, and low-power designSynthesis and physical design implicationsExperience with industry-standard EDA tools (Synopsys, Cadence)Experience with low-power methodologies (UPF/CPF)Strong debugging and problem-solving skillsPreferred QualificationsFamiliarity with advanced technology nodes and implementation challengesExperience with formal verification techniquesExperience with silicon bring-up and post-silicon debugCompensation & BenefitsAnticipated annual base salary for Member of Technical Staff: $200,000 - $250,000Stock option grantComprehensive benefits package including health, dental, vision, and 401(k)