Astera Labs in San Jose, CA, is hiring a Principal/ Sr.Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions.
You will own complex blocks from micro-architecture through silicon bring-up, drive RTL implementation, and collaborate with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen6/Gen7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5.
#J-18808-LjbffrPrincipal Digital Design Engineer — AI Connectivity Architect in san jose at Unknown Company
This position is listed as full time and onsite.