Implement, verify, and conduct timing closure to tape out Palladium and Protium SOCs
Lead a team to implement SOCs or sub-system chips
Work on RTL synthesis and floor planning
Build clock trees and perform optimizations
Close timing, IR drop and physical verification
Review and document designs for taping out
Interface with Front End RTL design teams and Back End Verification teams
Requirements
BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum of 1 year of experience
Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
Experience with advanced technologies like 5nm, 3ns and 2nm nodes
Experience using Linux servers
Script development using Shell/Perl/TCL
Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.