Principal ASIC Verification Engineer (SoC Lead)

Jariet Technologies, Inc. is seeking a principal ASIC functional verification engineer to design and implement verification test benches for high-speed digital SoCs.

The role may involve team leadership and close collaboration with the VLSI Design team to define verification strategies and plans. Ideal candidates will have extensive SystemVerilog/UVM experience, coverage methodology expertise, and strong written and verbal communication skills.