Unknown Company

Principal ASIC Engineer, Reliability, Hardware Validation

san jose, ca • Posted 5 days ago
Onsite Contract Engineering

  • • Lead the reliability and hardware design validation for next-generation semiconductor and networking products
  • • Bridge the gap between advanced semiconductor reliability testing and high-speed hardware board design
  • • Define and execute comprehensive product/process qualification plans for high-power solutions (wafer/package level)
  • • Drive robust, error-free HTOL, Burn-In, and stress testing (HAST, TC, HTS, ESD, LU, SER)
  • • Manage reliability suppliers and subcontractors to ensure adherence to qualification schedules
  • • Lead hardware design, schematic generation, and design validation for service provider routing products
  • • Manage board bring-up and debug processes
  • • Drive failure analysis activities and generate detailed qualification reports
  • • Partner with eCAD, FPGA, Power, Mechanical, Signal Integrity, and Manufacturing teams
  • • Provide technical documentation and support for customer quality and reliability requirements

Requirements

  • Master’s degree in electrical engineering, Computer Engineering, or a related field
  • 10+ years of professional experience in semiconductor reliability and/or high-speed hardware design
  • Proven experience in developing high-power HTOL/Burn-In testing for advanced node products
  • Deep knowledge of JEDEC, AEC, and Telcordia standards
  • Hands-on experience with high-speed network interfaces, board design
  • Familiarity with tools such as Cadence Allegro
  • Experience with high-speed measurement equipment and automated test development
  • Ability to interpret sophisticated schematics and layouts
  • Proficiency in data analysis/debug and HTOL set-up
  • PhD in Electrical or Computer Engineering (preferred)
  • Experience with 2nm/3nm Hyperscaler Multi-Chip-Modules and advanced packaging (CoWoS, SoIC, EMIB) (preferred)
  • Deep expertise in >100Gbps system design, signal integrity, and power distribution (preferred)
  • Knowledge of SerDes architecture (NRZ/PAM4 at 56G/112G/224G+) (preferred)
  • PCIe Gen5/6, and 800G Ethernet (preferred)
  • Proficiency in Python, Perl, TCL, or Verilog for scripting and automation (preferred)
  • Experience with JMP, Reliasoft, or Minitab for reliability statistical analysis (preferred)
  • Understanding of FMEA processes, risk assessment, and reliability lifetime modeling (preferred)

Core Competencies

Demonstrates expertise in semiconductor reliability testing and high-speed hardware design, with a strong focus on developing and executing qualification plans for high-power solutions. Proficient in managing cross-functional teams and ensuring compliance with industry standards while driving failure analysis and technical documentation.

Highest-signal resume keywords

  • Semiconductor Reliability Testing
  • High-Speed Hardware Design
  • HTOL/Burn-In Testing
  • Data Analysis/Debug
  • Signal Integrity

ATS Optimization Keywords

Hard Skills

  • Electrical Engineering
  • High-Power Solutions
  • Failure Analysis
  • Schematic Generation
  • Data Analysis
  • Reliability Testing
  • HTOL Set-Up
  • FMEA Processes
  • Risk Assessment
  • Reliability Lifetime Modeling

Industry Keywords

  • JEDEC Standards
  • AEC Standards
  • Telcordia Standards
  • 2nm/3nm Technology
  • Multi-Chip-Modules
  • CoWoS
  • SoIC
  • EMIB
  • PCIe Gen5/6
  • 800G Ethernet

Tools & Technologies

  • Cadence Allegro
  • High-Speed Measurement Equipment
  • JMP
  • Reliasoft
  • Minitab
  • Python
  • Perl
  • TCL
  • Verilog

#J-18808-Ljbffr
Back to Job Search