Define end-to-end verification strategy for large Satellite communication ASIC or SoC programs
Establish verification methodologies, infrastructure, and signoff criteria across block, subsystem, and SoC levels
Lead verification planning for complex communication functions such as modem pipelines, FEC engines, digital beamforming, packet processing, and control fabrics
Drive alignment among design, architecture, systems, firmware, and validation teams
Evaluate verification completeness through coverage, assertions, formal analysis, emulation, and silicon correlation
Resolve critical technical issues and direct root-cause analysis for the most complex functional failures
Guide development of reusable VIP, reference models, and regression automation frameworks
Mentor technical leaders and raise the overall verification maturity of the organization
Influence future verification roadmap, tool strategy, and reuse models
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
12+ years of ASIC/SoC verification experience
Expert-level knowledge of System Verilog, UVM, assertions, and verification signoff methodology
Proven success leading verification for complex chips or multiple tape-outs
Strong understanding of communication signal-processing hardware and system-level integration
Excellent technical leadership and cross-organizational communication skills
Deep expertise in Space based communications, digital modems, phased-array processing, or payload processing (preferred)
Experience with formal property verification, emulation, and performance validation (preferred)