SiTime Corp. in Santa Clara, CA seeks a Senior Layout Design Engineer to lead top‑chip and block‑level analog layout for CMOS/BiCMOS circuits. You will coordinate with offshore designers, mentor juniors, and help develop standard methodologies across sites.
You will develop floorplans, power distribution, and device‑matching layouts, verify DRC/LVS/ERC, and own chip‑level integration and tape‑out while advancing best practices.
#J-18808-LjbffrPrincipal Analog Layout Engineer - Equity Eligible in santa clara at Unknown Company
This position is listed as full time and onsite.