Celero Communications, Inc. is seeking an experienced Principal Analog Design Engineer in San Jose, CA.
You will architect and develop high-speed analog circuits for transceivers and related functions, lead layout supervision, and drive verification across CMOS processes. The role requires a Master’s or PhD in Electrical Engineering with 5+ years in analog design, strong fundamentals, and proficiency in Virtuoso/Spectre/ADE, as well as EM and high-frequency design knowledge.
#J-18808-LjbffrPrincipal Analog Design Engineer – High-Speed Interconnects in san jose at Unknown Company
This position is listed as full time and onsite.