Astera Labs seeks a Principal Digital RTL Engineer to architect and deliver high-performance AMS blocks as part of our connectivity silicon. You will own designs from specs through silicon bring-up, setting technical direction and mentoring engineers to ship production-ready solutions.
The role emphasizes leadership in design methodology, verification, and cross-functional collaboration across digital, system, and packaging teams in a fast-growing AI infrastructure company.
#J-18808-LjbffrPrincipal AMS RTL Engineer: High-Speed SerDes & PLLs in san jose at Unknown Company
This position is listed as full time and onsite.