Astera Labs is seeking an Advanced Packaging Engineer, Principal in San Jose, CA to lead R&D for next-generation photonics packaging for AI infrastructure. This senior IC packaging role sets technical direction, drives 2.1D/2.5D/3D integration, and guides wafer-, panel-, and die-level packaging flows with OSAT and materials partners.
You will develop packaging PDKs, ensure reliability, and advance EIC-to-PIC integration for NPO/CPO products, reporting to senior technical leadership.
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