Pre-Silicon Validation Engineer

Pre-Silicon Validation EngineerQualcomm Technologies, Inc.Engineering Group, Engineering Group > ASICS EngineeringJob SummaryWe are seeking a highly motivated and experienced Junior/Senior Emulation Engineer to support the development and validation of complex ASIC and FPGA-based designs. The ideal candidate will have a strong background in hardware emulation, RTL verification, system-level debugging, and software-hardware co-validation.

Experience leveraging AI-driven productivity tools and automation techniques for design verification and debug is highly desirable.Key ResponsibilitiesDevelop, deploy, and maintain ASIC/FPGA emulation environments for complex SoC designs.Port RTL designs onto industry-standard emulation platforms such as Cadence Palladium, Siemens Veloce, or FPGA prototyping systems.Work closely with RTL, verification, architecture, and software teams to enable early hardware/software co-validation.Develop testbenches, transactors, and verification infrastructure using SystemVerilog and C/C++.Analyze and debug functional, performance, and system-level issues in emulation environments.Create automation scripts and workflows using Python to improve productivity, regression execution, and debug efficiency.Collaborate with design teams to optimize designs for emulation performance and resource utilization.Develop methodologies for waveform analysis, signal tracing, and failure root-cause identification.Apply AI-assisted tools and techniques to accelerate verification, debug, data analysis, and engineering productivity.Generate technical documentation and present findings to cross-functional teams and leadership.Minimum RequirementsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.0-2+ years of experience in ASIC verification, FPGA prototyping, or hardware emulation.Strong expertise in: SystemVerilog, C/C++, Linux environment and shell scripting, Python programming, ASIC and FPGA Emulation platforms.Experience with RTL debugging, waveform analysis, and design verification methodologies.Knowledge of SoC architectures, bus protocols, and hardware/software interactions.Strong analytical and problem-solving skills.Preferred QualificationsExperience with Cadence Palladium, Protium, Siemens Veloce, or Synopsys ZeBu platforms.Familiarity with FPGA implementation flows using Xilinx or Intel FPGAs.Exposure to AI/ML technologies and AI-powered engineering tools.Knowledge of PCIe, CXL, DDR, Ethernet, or other high-speed interfaces.Experience with cloud-based compute environments and large-scale regression management.Desired SkillsSystemVerilogC/C++LinuxPythonASIC EmulationFPGA PrototypingSoC VerificationHardware/Software Co-ValidationDebug and Root Cause AnalysisAI-Assisted Engineering ToolsAutomation and ScriptingCross-Functional CollaborationPay range and Other Compensation & Benefits: $101,400.00 - $152,200.00