Pre-Silicon Memory Verification Engineer - Hybrid (UVM)

Solidigm in Rancho Cordova, CA seeks a pre-silicon verification engineer for advanced 3D NAND designs. You will implement UVM-based tests, define functional coverage, and develop SystemVerilog Assertions to ensure thorough validation of complex memory components.

The role involves building mixed-signal models and full-chip verification environments, plus automation tools to streamline workflows and data collection. Hybrid work arrangement in California is available.