Post-Silicon Memory Validation Lead (GDDR/LPDDR/HBM)

NVIDIA Corporation is seeking a senior memory engineer to lead high‑speed memory interface bring‑up and qualification on GPU/SoC silicon in Santa Clara, CA. You will own validation, IO tuning, timing margins, and multi‑vendor DRAM qualification across GDDR, LPDDR, and HBM.

You will design AI‑enabled workflows for margin analysis and failure triage, collaborate with pre‑Si teams and DV groups, and coordinate with DRAM vendors and manufacturing partners worldwide.