Job Details
Job Description: The Role and Impact: Join Intel as a Physical Design Engineering Graduate Intern and contribute to shaping the future of silicon innovation. This hands-on role is an exciting opportunity to be part of the physical implementation of state-of-the-art silicon designs that power Intel's cutting-edge technologies. You will work with a multidisciplinary team to optimize designs for manufacturability and performance, while developing critical skills and exploring pathways for career growth. As an intern, you will make impactful contributions to Intel's business goals and gain invaluable experience in a highly collaborative and learning-oriented environment.
Key Responsibilities
- Support physical design implementation processes, including synthesis, place-and-route, timing analysis, clocking, and/or integration.
- Assist in verification and signoff activities to ensure manufacturability and performance compliance of silicon designs.
- Collaborate with cross-functional teams to enhance design scalability and automation efforts.
- Apply design optimization techniques to improve power, performance, and area efficiency in silicon designs.
- Perform floor planning and clock tree synthesis to achieve robust physical designs.
- Contribute to static timing analysis to meet critical timing constraints for manufacturability.
- Explore innovative solutions for low-power design and power reduction strategies in physical design workflows.
- Embrace continuous learning and problem-solving to support Intel's commitment to advancing technology leadership.
Qualifications
Minimum Qualifications:
- Currently pursuing a master’s degree in electrical engineering or computer engineering, or a related technical specialized field.
- 3+ months of experience with the following skills: Proficiency in physical design tools and flows, including design planning tools, floor planning, and static timing analysis.
- Knowledge of low-power design techniques and power reduction methodologies.
- Familiarity with clock tree synthesis and design optimization principles.
- Demonstrated ability to analyze and solve complex technical problems.
Preferred Qualifications:
- Strong communication and collaboration skills to work effectively in cross-functional teams.
- Eagerness to explore and learn about design scalability, automation, and innovative approaches to physical design challenges.
- Passion for continuous improvement and self-driven development in a dynamic environment.
- Ability to adapt to new tools, techniques, and industry trends in silicon design.
Job Type
- Student / Intern
- Shift: Shift 1 (United States of America)
- Primary Location: US, California, Folsom
- Additional Locations: US, Arizona, Phoenix; US, California, Santa Clara
EEO Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.
Benefits
- Competitive pay
- Stock bonuses
- Benefit programs which include health, retirement, and vacation
Annual Salary Range
Annual Salary Range for jobs which could be performed in the US: $89, ,600.00 USD
Work Model
- This role will require an on-site presence.
- Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Additional Information
Intel’s official careers website.
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