Experience - 10-20 years, Salary: On-site/Hybrid
Required Skills
- 5+ years of experience in physical design.
- A good grasp of RTL2GDS flow and design tapeouts in 3nm or smaller process technology.
- Experience with Synopsys EDA tools like FusionCompiler and Primetime.
- Experience with custom or regular clock tree synthesis (block or top level) and techniques to reduce clock power.
- Experience with low-power implementation, power gating, multiple voltage rails, and UPF knowledge.
- Experience with PTPX power flow.
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