- Good understanding of Cadence tools (Innovous, Quantus, Voltus).
- Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.
- Experience in developing and implementing Power-grid and high-speed clock constraints and specifications.
- Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.
- Experience with CDC, static timing analysis methodologies and relevant tools.
- Understanding and experience of mixed signal environments is a must.
- Candidates must be familiar with Caliber & Redhawk (power analysis) tools.
- Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development.
Physical Design Engineer in san jose at Unknown Company
This position is listed as full time and onsite.