Good understanding of Cadence tools (Innovous, Quantus, Voltus).
Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floor planning, CTS and place and route.
Experience in developing and implementing Power-grid and high speed clock constraints and specifications.
Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.
Experience with CDC, static timing analysis methodologies and relevant tools.
Understanding and experience of mixed signal environments is a must.
Candidates must be familiar with Caliber & Redhawk (power analysis) tools.
Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development.
Participate in yield analysis, drive necessary improvement actions on silicon process, setting optimization, and testing robustness to improve yield to target
Work with reliability engineers to achieve successful product qualifications based on JEDEC and AECQ100 Standards
Failure analysis support for customer returned issue
Preferred Qualification
Requires BE/B.Tech degree in Electrical / Electronic with 1 to 8 years of Semiconductor Product engineering experience.
Experience working with CMOS ASIC Design, Test, Foundry & Production teams.
Strong track record of ASIC design from concept to mass production all the way to EOL.
Deep understanding of statistical data analysis along with data analysis tools such as Excel VBA / Spotfire / O+ / JMP / Galaxy.
Should have basic to advance Knowledge of the ATE Tester, V93K is preferred.
Strong analytical skills, ability to problem solve and debug systems, circuits, and devices.
Experienced in product coordination, yield improvement & test time reduction.
Working knowledge of semiconductor quality and automotive standard process control
Hands-on experience with production & Characterization data collection at Wafer as well as Package level
Experience in working in production test floors, bench instruments & ATE is a plus.