Insight Global is seeking a Physical Design Lead to join a cutting-edge Silicon Technology Engineering team developing advanced-node mixed-signal ASICs for next-generation SoC and memory test platforms.
In this technical leadership role, you'll drive RTL-to-GDSII execution , lead physical design strategy, mentor engineers, and collaborate with cross-functional teams to deliver high-quality silicon at advanced process nodes.
Key Responsibilities:
- Lead physical design efforts from architecture through signoff
- Own floorplanning, timing closure, power planning, and physical implementation
- Drive synthesis, STA, CDC, LEC, and signoff activities
- Integrate complex IP including PCIe, DDR5/DDR6, UFS, and SerDes
- Collaborate with internal teams and external design partners
- Develop and improve PD automation and tool flows
Required Qualifications:
- 10+ years of ASIC Physical Design experience
- Experience at advanced nodes (16nm and below)
- Strong expertise in RTL-to-GDSII flows and timing closure
- Deep knowledge of STA, constraints development, and signoff methodologies
- Experience with Cadence EDA tools and scripting (Tcl, Python, Make)
- BS/MS in Electrical Engineering or equivalent experience
Join a team at the forefront of semiconductor innovation and help deliver first-pass success on complex, advanced-node ASIC programs.
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This position is listed as full time and onsite.