We need a skilled Physical Design Engineer to turn complex chip plans into real silicon. You will work on high-speed designs using advanced technology nodes. Your main job is to push PPA limits while ensuring complete sign-off readiness.
Title: Physical Design Engineer
Location: Onsite to Mountain View, CA
Duration: Contract/Full time
Experience:8+ Years
Key Responsibilities
- Place and Route (PPR): Run full-chip and block-level floorplanning, placement, clock tree synthesis (CTS), and routing using industry tools.
- Timing Closure: Fix setup, hold, and DRC violations to meet tight timing goals.
- PPA Optimization: Balance power, performance, and area to meet product specs.
- Physical Verification: Run LVS, DRC, and antenna checks to ensure design manufacturing safety.
- Low Power Design: Implement multi-voltage and power-gating techniques.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- 3 to 8 years of hands-on chip design experience.
- Strong knowledge of industry tools from Synopsys, Cadence, or Siemens EDA.
- Good scripting skills in Tcl, Perl, or Python.
- Deep understanding of sub-micron technology node
Physical Design Engineer in mountain view at Unknown Company
This position is listed as contract and onsite.