Physical Design Engineer: High-Speed SoC & Power

Qualcomm Atheros, Inc. in Santa Clara, CA is seeking a Physical Design Engineer to join the Connectivity SoC team.

You will work on the complete physical design flow for high-speed, low-power designs, including floorplanning, place-and-route, power planning, IR drop analysis, timing closure, and ECOs. Proficiency with Python and shell scripting, and experience with Cadence Innovus or Synopsys Fusion Compiler is required.