Physical Design Engineer — End-to-End Chip Timing

LanceSoft, Inc. in San Jose, CA is seeking a Physical Design Engineer to lead end-to-end physical design activities for complex digital designs. The role emphasizes hands-on synthesis, PnR, and timing closure in advanced process nodes, with collaboration across design, packaging, and test teams.

The ideal candidate has 5+ years in physical design, strong experience with Cadence/Synopsys tool flows, and a track record of tapeouts on 7nm and below, including SOC/ASIC/GPU/CPU design contexts.