Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
Execute comprehensive physical design flows, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
Conduct verification and signoff activities such as formal equivalence verification, static timing analysis, power integrity analysis, and layout verification.
Analyze results to identify and resolve violations related to timing, reliability, and design structure.
Optimize designs for power, performance, and area using industry-standard EDA tools.
Develop and refine physical design methodologies and flow automation to improve team efficiency and accuracy.
Collaborate with teams to address design challenges and deliver robust solutions.
Requirements
Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, and 3+ years of experience in physical design; OR a Master's degree in Electrical Engineering, Computer Engineering, or a related field, and 2+ years of experience in physical design; OR a PhD in Electrical Engineering, Computer Engineering, or a related field.
In RTL-to-GDS implementation, including synthesis, place and route, and timing closure.
In industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics for physical design tasks.
In static timing analysis, floor planning, and power integrity analysis.
Strong knowledge of low-power design techniques and methodologies.