Overview
We are seeking expert Physical Design Engineers to lead top-level signoff activities for complex SoCs on advanced nodes (7nm / 5nm / 3nm ). The ideal candidate will have multiple full-cycle tapeouts and the technical depth to independently drive signoff-to-tapeout closure. This role requires close collaboration with RTL, Timing, Power Integrity, and Foundry teams to ensure structural integrity, timing convergence, and power reliability for high-performance silicon.
Core Responsibilities
- Lead top-level signoff for high-performance SoC designs.
- Collaborate with RTL, Physical Design, STA, and Foundry teams.
- Execute, analyze, and debug complex full-chip design challenges.
- Develop and optimize signoff methodologies to improve TAT (Turn-Around Time) and PPA (Power, Performance, Area) .
- Identify and mitigate timing, power, reliability, and clocking risks at full-chip level.
- Drive signoff closure and tapeout readiness independently.
Specialized Expertise
Subject Matter Experts in at least one track
Track 1: Top-Level Clock Distribution
- Design and analyze clock architectures (H-Tree, Mesh, Hybrid).
- Drive CTS for ultra-low skew and balanced latency.
- Optimize clock power with advanced gating techniques.
- Validate clock signal integrity and duty cycle distortion (DCD).
- Tools: Cadence Innovus, Synopsys ICC2, specialized CTS engines.
Track 2: Physical Verification (PV)
- Own end-to-end PV signoff closure across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
- Debug complex PV violations across layout, routing, macros, IP, power grid, decks, and tool/setup issues.
- Build repeatable tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.
- Tools: Pegasus, Calibre.
Track 3: Top-Level EMIR (Power Integrity)
- Perform full-chip Static & Dynamic IR Drop analysis.
- Execute Electromigration (EM) verification.
- Optimize PDN for reliability and noise margins.
- Analyze high-frequency switching impacts and voltage droop behavior.
- Drive power integrity signoff closure.
- Tools: Ansys RedHawk-SC, Cadence Voltus, equivalent EMIR tools.
Required Qualifications
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of experience in Physical Design/Signoff.
- Proven track record with 2–3 successful tapeouts on advanced nodes (7nm, 5nm, 3nm).
- Deep knowledge of OCV, AOCV/POCV, and statistical timing methodologies.
- Strong expertise in top-level signoff methodologies.
- Proficiency in scripting and automation (Tcl, Python, Perl).
- Excellent debugging, analytical, and communication skills.
- Ability to present signoff status, risks, and closure plans to leadership.
Preferred Skills
- Experience with 2.5D/3D IC packaging signoff .
- Familiarity with foundry signoff methodologies (TSMC, Samsung, Intel).
- Prior experience in HPC, AI accelerators, or large-scale SoC designs.