- Strong hands-on experience in full physical design flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff
- Strong proficiency with Synopsys or Cadence tools (ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)
- Strong experience in physical design implementation for complex GPU or SoC designs, including low-power design and physical verification (DRC/LVS)
- Experience with timing analysis and closure methodologies, including STA and signal integrity
- Experience with advanced node design (≤5nm), including congestion, IR drop, and variability considerations
- Strong proficiency in scripting and automation (Python, Tcl, Shell, Perl)
- Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach
- Excellent written and verbal communication skills for documenting designs, methodologies, and best practices
- Excellent collaboration skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment
Preferred Qualifications
- Experience with block-level implementation on complex SoC designs
- Exposure to advanced nodes (≤5nm)
- Exposure to GPU or high-performance compute architectures