ACL Digital is seeking a PCIe verification engineer in San Jose, CA to verify a Gen6 subsystem using SystemVerilog/UVM. You will develop plans, testbenches, cases, and coverage, and ensure protocol compliance across LTSSM, link training, and power management.
Work with RTL, Architecture, and Validation teams to drive regression suites, debug issues, and achieve coverage closure for a complex PCIe design.
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