We’re looking for an architect to lead the design and implementation of the inter-wafer scale-up network. Connecting very high bandwidth and high capacity wafers into a “super-system” will enable previously unprecedented capabilities for the AI industry.
Ideal Background:
- Deep knowledge of networks, especially knowledge of tradeoffs and advantages of different network topologies for different workloads and applications
- Understanding and ideally experience in implementation of network protocols
- Understanding of AI workloads and their network design implications (eg message sizes vs latency, bandwidth, hops, etc)
Nice to Have:
- Hands-on experience with architecture and design process of either switch or NIC chips
- Experience in tradeoffs between different network protocols for AI applications
- Experience in large-scale AI clusters
- Experience in large-scale optical network fabrics, especially with issues around reliability/RAS